2-12. RECEIVE DATA SIGNAL PATH. Continued
The signals are amplified to the correct levels and output to the RT AUD/DATA connector (J4). DIGITAL DATA
RCV (DDR) and DIGITAL DATA CLK OUT (DDCO) output signal levels are 5 V for logic 0 and -5 V for logic 1.
Analog data signal levels are 0.77 Vrms ±3 dB.
When operating in FH mode, data received signals are routed through the ECCM module. The switching module
sends the bit synchronized data (BS DATA) to the ECCM module for deinterleaving. FH DATA is returned to the
data receive path.
Receive data cipher text (RDCT) is routed to the COMSEC module from the switching module when the RT
operates in cipher text mode.
The COMSEC module decodes the signal and returns the data receive signal
(AR/DDR) to the ICOM control module. The COMSEC module generates a clock signal for the data (AT/DDCO)
and routes this to the ICOM control module also.
Each data transmission is preceded by a sync preamble. This preamble is generated by the data rate adapter
section of the ICOM control module. It provides a synchronization source, tells the RT a data transmission is
being received, and whether the signal is plain or cipher text. During receive mode, the data rate adapter section
monitors the RCV DATA signal and notifies the rest of the ICOM control module when the preamble is detected.
When the data rate is set to TF or one of the other data rates, the ICOM control module sends the signals to the
data rate adapter section of the ICOM control module (RCV DATA and RCV CLK). The data and clock signals are
converted to LO-SPD DATA and LO-SPD CLK. LO-SPD DATA SEL-N at logic 0 switches these LO-SPD signals
back into their proper paths.
The TF signal is tapped from the LO-SPD DATA line. It is shaped by an RC circuit into the necessary analog signal
by the ICOM data I/O module.
2-13. TRANSMIT DATA SIGNAL PATH.
The RT can process analog data and digital data. Analog data is input on J4 pin D (AT/DDCO). See figure FO-6.
If the data rate is set to TF, J4 pin F (ADMC/DDT) must be grounded for proper operation. The analog data signal
will be converted to 16 kb/s digital data by the RT. If the data rate is set to AD1, the signal follows the audio path.
Digital data is input on J4 pin F (ADMC/DDT). Pin E (DDMC) must be grounded. The RT provides a clock on J4
pin D (DDCO) and the digital data signal must be synchronized with the clock.
For TF, the analog data signal must be FSK modulated at 1200/2400 Hz. It is routed through the ICOM data I/O
module. An AGC amplifier and limiter adjust the level and the signal is output as LIMITED ANALOG DATA. The
ICOM control module demodulates the FSK signal to convert it into a low speed digital signal. This signal is routed
through the data rate adapter section of the ICOM control module where it is converted into a 16 kb/s digital data
stream (XMT DATA). It is routed to the ICOM power supply where the signal is buffered and then routed through
the switching module to the exciter/power amplifier.
The digital data transmit (DDT) signal will be input as a ±5 V square wave. It is converted to logic 0/1 levels by
the ICOM data I/O module. The logic 0/1 level signal (DIGITAL DATA XMT) is routed to the ICOM control module.
If it is anything other than 16 kb/s, it is routed to the data rate adapter section, It converts the data rate to 16 kb/s
and returns the signal.
The signal is routed to the ICOM power supply where it is buffered and sent to the
switching module. The switching module routes the signal to the exciter/power amplifier.
In the FH mode, the BS DATA signal in the switching module is sent to the ECCM module for interleaving. The FH
DATA signal is returned to the switching module to continue the data signal path.
In the cipher text mode, the DIGITAL DATA signal in the ICOM control module is routed to the COMSEC module.
The COMSEC device encrypts the signals and returns the VIN CT XMT signal.
The digital data clock out (DDCO) originates in the switching module (PT DIGITAL CLK-R), the COMSEC module
(CT DIGITAL CLK), or the data rate adapter section of the ICOM control module (LO SPD CLK).