OVERALL FUNCTIONAL DESCRIPTION. Continued
Power Amplifier Block Diagram.
INPUT CONTROL SIGNAL PATHS.
The power amplifier requires four control signals from the RT. See figure FO-16. When the RTRF switch is set to
PA, the HIGH POWER XMT line is set to logic 1. One of three filter lines will also be set to logic 1 depending on the
frequency. The power amplifier frequency bands are as follows:
Frequency Band (MHz)
30 to 43
43 to 61.5
61.5 to 88
The decoder control (6A2) drives the switching FET. When the HIGH POWER XMT line is set to logic 1, the
TRANSMIT output line is set to 13 V dc (1 2.5 to 13.5 V dc). The RECEIVE line is the opposite. When the HIGH
POWER XMT line is at 0 V dc, the RECEIVE line is set to 13 V dc. When the gate (G) of a switching FET is held at 13
V dc, current flows from the source (S) to the drain (D). In the power amplifier case (6A1), the drain of the FET is
held at 200 V dc when the FET is not conducting. When the FET conducts, the voltage drops to near 0 V. The 0 V
level sets the electronic switches in the input and output filter switches (6A1A2 and 6A1A1). The filters (all except
FL14) are used to isolate the RF energy.
The FILTER A, FILTER B, and FILTER C paths operate in the same way. The logic level from the RT is converted to
0 or 13 V dc by the decoder control. The output of the decoder control drives the switching FET. The output from
the FET sets the input and output filter switch.